Voids in Bottom Termination Components (BTC)

The market for Bottom Termination Components (BTCs) representative of QFN and DFN package is rapidly increasing in the electronic industry as the key drivers are - miniaturization and costs.

BTC's have brought new challenges in design and assembly processes, when these package types were introduced in the market. The large areas of the solder terminals bring many advantages with them, like dissipating heat of the component. However, if the assembly process is not properly adjusted than this can cause voids under the component. The amount of voids can be influenced by different adjustments such as solder pastes with special solvents and grain sizes, thickness of solder paste print on land pattern, the solder profile, the land pattern design, the solder stencil design and the surface of the PCB. This application note was created with respect to work carried out to evaluate the challenges of voids on the WE-MAPI (DFN) products. Various techniques were implemented and tests were carried out, in order to resolve this issue such as - custom land pattern designs, optimization of reflow profile, custom stencils, push off tests etc. A brief description of the findings, techniques and tests implemented are discussed in this report.

Summary

The main agenda of avoiding lake voids in our bottom termination components (BTC) with a dual flat package was successively achieved. There was no decrease in the solder joint strength, rather a dramatic increase in the same (from 60 N to 120 N approx.). Using a vacuum reflow oven or any other non-oxygen medium reflow, will help in voids reduction to a large extent.

All in all, voids are a boon as much as they are bane (like friction for instance). One should fathom the fact, that voids are an unavoidable phenomena when it comes to the bonding of two different metals in a molten state, in a non-vacuum environment. They basically act as stress absorbers or relievers and avoid the propagation of cracks within the solder joints. Complete absence of voids will actually result in higher tension in the joints eventually leading to developments of cracks in the joints. What can only be of concern are the lake voids. These trap air and act as thermal insulators. This in turn leads to a faster increase of the effective temperature rise of the component and a decrease in the overall solder joint strength. These lake voids were effectively eliminated without influencing any electrical parameters such as DCR, rated current, saturation current etc., by the techniques discussed in this application note.

Download: ANP036