Microchip dsPIC33EP64GS502 | Demoboard 750W-AC-DC

Beschreibung

Microchip’s 750W AC-DC Reference Design demonstrates a semi-bridgeless PFC topology followed by a peak current controlled zero-voltage switching full-bridge (ZVS FB) converter with digital slope compensation to achieve very high conversion efficiencies. This power supply can be firmware updated (including the compensator algorithm) with zero down time to the system it is powering while the power supply is running. It is implemented using two dsPIC33EP “GS” digital-power DSCs that provide full digital control of the power conversion as well as all system management functions.The ZVS FB Converter is designed to stepdown an input DC voltage of 400V to an output DC voltage of 12V. A unique feature of the reference design is the implementation of peak current control, using a fully software-based slope compensation algorithm, which eliminates the use of external analog components for slope compensation. The 750W AC/DC Reference Design is royalty free when used in accordance with the licensing agreement.

Eigenschaften

• 3.0V to 3.6V, -40°C to +85°C, DC to 70 MIPS
• 3.0V to 3.6V, -40°C to +125°C, DC to 60 MIPS Flash Architecture
• 16K Flash Program Memory
• Core: 16-Bit dsPIC33E CPU
• Two 40-Bit Wide Accumulators
• Code-Efficient (C and Assembly) Architecture
• Single-Cycle (MAC/MPY) with Dual Data Fetch
• Single-Cycle Mixed-Sign MUL Plus Hardware Divide
• 32-Bit Multiply Support
• Two Additional Working Register Sets (reduces context switching) High-Speed PWM
• Individual Time Base and Duty Cycle for each PWM
• 1.04 ns PWM Resolution (frequency, duty cycle, dead time and phase)
• Supports Center-Aligned, Redundant, Complementary and True Independent Output modes
• Independent Fault and Current-Limit Inputs
• Output Override Control
• PWM Support for AC/DC, DC/DC, Inverters, PFC and Lighting
• Advanced Analog Features
• High-Speed ADC module
• 12-bit with 4 dedicated SAR ADC cores and one shared SAR ADC core
• Configurable resolution (up to 12-bit) for each ADC core
• Up to 3.25 Msps conversion rate per channel at 12-bit resolution
• Dedicated result buffer for each analog channel
• Flexible and independent ADC trigger sources
• Two digital comparators
• Two oversampling filters for increased resolution
• ADC with Early Interrupt feature
• Four Rail-to-Rail Comparators with Hysteresis
• Dedicated 12-bit Digital-to-Analog Converter (DAC) for each analog comparator
• DAC reference outputs
• External reference inputs
• Two Programmable Gain Amplifiers
• Single-ended or independent ground reference
• Five selectable gains (4x, 8x, 16x, 32x and 64x)
• 40 MHz gain bandwidth Interconnected SMPS Peripherals
• Reduces CPU Interaction to Improve Performance
• Flexible PWM Trigger Options for ADC Conversions
• High-Speed Comparator Truncates PWM (15 ns typical)
• Supports Cycle-by-Cycle Current mode control
• Current Reset mode (variable frequency)
• Timers/Output Compare/Input Capture
• 16-Bit and up to Two 32-Bit Timers/Counters
• Output Compare (OC) modules, Configurable as Timers/Counters
• Input Capture (IC) modules
• Functional Safety support (ISO26262)
• ASIL-B & ASIL-C focused applications
• FMEDA and Safety manual available under NDA upon request to your sales office
• Safety qualified XC16 compiler
• Functional Safety hardware features
• Multiple redundant clock sources
• IO ports read-back
• Analog peripherals redundancies
• Windowed Watchdog Timer
• Hardware traps
• SFR locks
• Write protection

Typische Anwendungen

• General application AC/DC

Weiterführende Informationen

• Datenblatt
• Produktseite des IC-Herstellers