Intel 5AGTFD7K3F40I3N

Beschreibung

The Arria V GT FPGA development board provides a hardware platform fordeveloping and prototyping low-power, high-performance, and logic-intensive designs using Altera’s Arria V GT FPGA device. The board provides a wide range of peripherals and memory interfaces to facilitate the development of Arria V GT FPGA designs.Two high-speed mezzanine card (HSMC) connectors are available to add additional functionality via a variety of HSMCs available from Altera® and various partners.

Eigenschaften

• Two Arria V GT FPGA 5AGTFD7K3F40I3N in the 1517-pin FineLine BGA (FBGA)package
• 504K LEs
• 190,240 adaptive logic modules (ALMs)
• 24,140 Kbit (Kb) M10K on-die memory
• 2,906 Kb MLAB memory
• 36 transceivers
• 16 phase locked loops (PLLs)
• 2,312 18x18 multipliers
• 1.15-V core voltage
• MAX® II CPLD EPM2210GF324 System Controller in the 324-pin FBGA package
• FPGA configuration circuitry
• MAX II CPLD EPM570GM100 and flash fast passive parallel (FPP)configuration
• On-board USB-BlasterTM II for use with the Quartus® II Programmer
• Clocking circuitry
• Nine on-board oscillators
• One 50-MHz oscillator
• Two 125-MHz oscillators
• Clock buffer with six outputs sourced by SMA or programmable oscillatorwith a default frequency of 100-MHz
• One programmable oscillator with a default frequency of 148.5-MHz
• Four programmable oscillators with four outputs each of various defaultfrequencies
• Clock buffer with two outputs sourced by one of the above fourprogrammable oscillators with one output to the FPGA reference clock andBull's Eye® SMA
• SMA connectors for external LVPECL clock input
• Power supply
• 14-V – 20-V DC input
• PCI Express edge connector power
• 12-V PCI Express ATX supply
• On-board power measurement circuitry
• Mechanical
• PCI Express long form factor (4.376” x 10.45”)
• PCI Express chassis or bench-top operation

Weiterführende Informationen

• Datenblatt
• Produktseite des IC-Herstellers