Topologie | Sonstige Topologie |
IC-Revision | 1.0 |
The DEO-Nno-SOC Development kit presents a robust hardware design plateform built around the altera system on chip FPGA, which combines the latest dual-core cortex-A9 embedded cores with industry-leading peogrammable logic for ultimate desigen flexibility.
Muster |
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Artikel Nr. | Datenblatt | Simulation | Downloads | Status | Produktserie | λDom typ. (nm) | Farbe | λPeak typ. (nm) | IV typ. (mcd) | VF typ. (V) | Chiptechnologie | 2θ50% typ. (°) | Anwendung | Betriebstemperatur | L (µH) | IRP,40K (A) | ISAT,30% (A) | RDC typ. (mΩ) | fres (MHz) | VOP (V) | Interface typ | IR 1 (mA) | Poles | L (mm) | Dampfphasenprozess | Z @ 100 MHz (Ω) | Zmax (Ω) | Testbedingung Zmax | IR 2 (mA) | RDC max. (Ω) | Typ | Pins (Value) (pcs) | Reihen | H (mm) | Gender | IR (mA) | Verpackung | Raster (mm) | Version | Montageart | Arbeitsspannung (V (AC)) | Kontaktwiderstand (mΩ) | Tol. R | Muster |
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