Topology | Other Topology |
IC revision | 1.0 |
The DEO-Nno-SOC Development kit presents a robust hardware design plateform built around the altera system on chip FPGA, which combines the latest dual-core cortex-A9 embedded cores with industry-leading peogrammable logic for ultimate desigen flexibility.
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Order Code | Datasheet | Simulation | Downloads | Status | Product series | λDom typ. (nm) | Emitting Color | λPeak typ. (nm) | IV typ. (mcd) | VF typ. (V) | Chip Technology | 2θ50% typ. (°) | Operating Temperature | L (µH) | IRP,40K (A) | ISAT,30% (A) | RDC typ. (mΩ) | fres (MHz) | VOP (V) | Application | Interface Type | IR (mA) | Poles | L (mm) | Vaporphase process | Z @ 100 MHz (Ω) | Zmax (Ω) | Test Condition Zmax | IR 2 (mA) | RDC max. (Ω) | Type | Pins (Value) (pcs) | Rows | H (mm) | Gender | IR (mA) | Packaging | Pitch (mm) | Mount | Working Voltage (V (AC)) | Contact Resistance (mΩ) | Tol. R | Samples |
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