Microchip AT91SAM9XE-EK

Description

Incorporates the ARM926EJ-S™ ARM® Thumb® Processor– DSP instruction Extensions, ARM Jazelle® Technology for Java® Acceleration– 8 Kbyte Data Cache, 16 Kbyte Instruction Cache, Write Buffer– 200 MIPS at 180 MHz– Memory Management Unit– EmbeddedICE™, Debug Communication Channel Support• Additional Embedded Memories– One 32 Kbyte Internal ROM, Single-cycle Access at Maximum Matrix Speed– One 32 Kbyte (for AT91SAM9XE256 and AT91SAM9XE512) or 16 Kbyte (for AT91SAM9XE128) Internal SRAM, Single-cycleAccess at Maximum Matrix Speed– 128, 256 or 512 Kbytes of Internal High-speed Flash for AT91SAM9XE128, AT91SAM9XE256 or AT91SAM9XE512Respectively. Organized in 256, 512 or 1024 Pages of 512 Bytes Respectively.• 128-bit Wide Access• Fast Read Time: 60 ns• Page Programming Time: 4 ms, Including Page Auto-erase,Full Erase Time: 10 ms• 10,000 Write Cycles, 10 Years Data Retention, Page Lock Capabilities, Flash Security Bit• Enhanced Embedded Flash Controller (EEFC)– Interface of the Flash Block with the 32-bit Internal Bus– Increases Performance in ARM and Thumb Mode with 128-bit Wide Memory Interface• External Bus Interface (EBI)– Supports SDRAM, Static Memory, ECC-enabled NAND Flash and CompactFlash™• USB 2.0 Full Speed (12 Mbits per second) Device Port– On-chip Transceiver, 2,688-byte Configurable Integrated DPRAM• USB 2.0 Full Speed (12 Mbits per second) Host Single Port in the 208-pin PQFP Device and Double Port in 217-ball LFBGADevice– Single or Dual On-chip Transceivers– Integrated FIFOs and Dedicated DMA Channels• Ethernet MAC 10/100 Base-T– Media Independent Interface or Reduced Media Independent Interface– 28-byte FIFOs and Dedicated DMA Channels for Receive and Transmit• Image Sensor Interface– ITU-R BT. 601/656 External Interface, Programmable Frame Capture Rate– 12-bit Data Interface for Support of High Sensibility Sensors– SAV and EAV Synchronization, Preview Path with Scaler, YCbCr Format• Bus Matrix– Six 32-bit-layer Matrix– Remap Command3-2 AT91SAM9XE-EK Evaluation Board User Guide6311A–ATARM–04-Feb-08• Fully-featured System Controller, including– Reset Controller, Shutdown Controller– Four 32-bit Battery Backup Registers for a Total of 16 Bytes– Clock Generator and Power Management Controller– Advanced Interrupt Controller and Debug Unit– Periodic Interval Timer, Watchdog Timer and Real-time Timer• Reset Controller (RSTC)– Based on a Power-on Reset Cell, Reset Source Identification and Reset Output Control• Clock Generator (CKGR)– Selectable 32,768 Hz Low-power Oscillator or Internal Low Power RC Oscillator on Battery Backup Power Supply,Providing a Permanent Slow Clock– 3 to 20 MHz On-chip Oscillator, One Up to 240 MHz PLL and One Up to 100 MHz PLL• Power Management Controller (PMC)– Very Slow Clock Operating Mode, Software Programmable Power Optimization Capabilities– Two Programmable External Clock Signals• Advanced Interrupt Controller (AIC)– Individually Maskable, Eight-level Priority, Vectored Interrupt Sources– Three External Interrupt Sources and One Fast Interrupt Source, Spurious Interrupt Protected• Debug Unit (DBGU)– 2-wire UART and support for Debug Communication Channel, Programmable ICE Access Prevention• Periodic Interval Timer (PIT)– 20-bit Interval Timer Plus 12-bit Interval Counter• Watchdog Timer (WDT)– Key-protected, Programmable Only Once, Windowed 16-bit Counter Running at Slow Clock• Real-Time Timer (RTT)– 32-bit Free-running Backup Counter Running at Slow Clock with 16-bit Prescaler• One 4-channel 10-bit Analog to Digital Converter• Three 32-bit Parallel Input/Output Controllers (PIOA, PIOB, PIOC,)– 96 Programmable I/O Lines Multiplexed with up to Two Peripheral I/Os– Input Change Interrupt Capability on Each I/O Line– Individually Programmable Open-drain, Pull-up Resistor and Synchronous Output• Peripheral DMA Controller Channels (PDC)• Two-slot Multimedia Card Interface (MCI)– SDCard/SDIO and MultiMediaCard™ Compliant– Automatic Protocol Control and Fast Automatic Data Transfers with PDC• One Synchronous Serial Controllers (SSC)– Independent Clock and Frame Sync Signals for Each Receiver and Transmitter– I²S Analog Interface Support, Time Division Multiplex Support– High-speed Continuous Data Stream Capabilities with 32-bit Data Transfer• Four Universal Synchronous/Asynchronous Receiver Transmitters (USART)– Individual Baud Rate Generator, IrDA® Infrared Modulation/Demodulation– Support for ISO7816 T0/T1 Smart Card, Hardware Handshaking, RS485 Support– Full Modem Signal Control on USART0• One 2-wire UART• Two Master/Slave Serial Peripheral Interface (SPI)– 8- to 16-bit Programmable Data Length, Four External Peripheral Chip Selects– Synchronous Communications• Two Three-channel 16-bit Timer/Counters (TC)– Three External Clock Inputs, Two Multi-purpose I/O Pins per Channel– Double PWM Generation, Capture/Waveform Mode, Up/Down Capability– High-Drive Capability on Outputs TIOA0, TIOA1, TIOA2AT91SAM9XE-EK Evaluation Board User Guide 3-36311A–ATARM–04-Feb-08• Two Two-wire Interfaces (TWI)– Master, Multi-master and Slave Mode Operation– General Call Supported in Slave Mode– Connection to PDC Channel to Optimize Data Transfers in Master Mode Only• IEEE® 1149.1 JTAG Boundary Scan on All Digital Pins• Required Power Supplies:– 1.65V to 1.95V for VDDBU, VDDCORE and VDDPLL– 1.65V to 3.6V for VDDIOP1 (Peripheral I/Os)– 3.0V to 3.6V for VDDIOP0 and VDDANA (Analog-to-digital Converter)– Programmable 1.65V to 1.95V or 3.0V to 3.6V for VDDIOM (Memory I/Os)• Available in a 208-pin PQFP Green and a 217-ball LFBGA Green Package

Features

– Reset Controller, Shutdown Controller

– Four 32-bit Battery Backup Registers for a Total of 16 Bytes

– Clock Generator and Power Management Controller

– Advanced Interrupt Controller and Debug Unit

– Periodic Interval Timer, Watchdog Timer and Real-time Timer

Typical applications

• Audio
• Remote Communication
• Microcontroller

More information

• Datasheet
• IC product information