Texas Instruments AFE8092 | Demoboard AFE8092EVM

Description

The AFE8092 evaluation module (EVM) is an RF-sampling transceiver platform that can be simultaneously configured to support up to eight-transmit eight-receive plus two-feedback (8T8R + 2FB) channels. AFE8092EVM evaluates the AFE8092, which belongs to a family of octal-channel, RF-sampling, analog front ends (AFEs) with 14-bit, 12-GSPS digital-to-analog converters (DACs), 14-bit, 4-GSPS analog-to-digital converters (ADCs), and an on-chip integrated phased-locked loop/voltage-controlled oscillator (PLL/VCO) for high-frequency clock generation in DACs and ADCs. AFE8092EVM has the option to use dual digital up and down converters in each channel to simultaneously synthesize and digitize multiple wideband signals with high dynamic range. An on-chip integrated digital step attenuator (DSA) for the receiver channels and DSA functionality for the transmitter channels is supported. Eight JESD204B/C-compatible serializer/deserializer (SerDes) transceivers running up to 32.5 Gbps can be used for providing inputs and outputs to and from the AFE8092 through the onboard FPGA mezzanine card (FMC) connector. AFE8092EVM includes the LMK04828 clock generator for providing a reference signal to the AFE on-chip PLL and for generating the required SYSREF signals for the JESD204B/C protocol. Also included is the option for providing an ultra-low-phase noise external clocking solution. AFE8092EVM implements an efficient power-management solution for the required power rails to the AFE. The design interfaces with the TI pattern/capture card solution (TSW14J58EVM, sold separately), as well as many FPGA development kits.

Features

• Evaluation of 8T8R + 2FB RF-sampling AFE80xx family of transceiver solutions, such as AFE8092
• JESD204B/C data interface to simplify digital interface; compliant up to 32.5-Gbps lane rates
• Supports JESD204B/C for synchronization and compatibility
• Includes efficient power-management solution
• Onboard clocking solution supported with LMK04828 and for generating SYSREF
• On-chip interpolation/decimation filter inputs/outputs sample data at reduced sample rates and improved signal-to-noise ratio (SNR)

More information

• Datasheet