Texas Instruments ADC09QJ1300-Q1 | Demoboard ADC12QJ1600EVM

Description

ADC09QJ1300-Q1 is a quad channel, 9-bit, 1.3 GSPS analog-to-digital converter (ADC). Low power consumption, high sampling rate and 9-bit resolution makes the ADC09QJ1300-Q1 ideally suited for light detection and ranging (LiDAR) systems and handheld test equipment. ADC09QJ1300-Q1 qualified for automotive applications.Full-power input bandwidth (-3 dB) of 6 GHz provides flat frequency response for frequency modulated continuous wave (FMCW) LiDAR systems and provides a narrow impulse response for pulse-based systems. The full-power input bandwidth also enables direct RF sampling of up to 4 GHz.A number of clocking features are included to relax system hardware requirements, such as an internal phase-locked loop (PLL) with integrated voltage-controlled oscillator (VCO) to generate the sampling clock. Four clock outputs are provided to clock the logic and SerDes of the FPGA or ASIC. A timestamp input and output is provided for pulsed systems.JESD204C serialized interface decreases system size by reducing the amount of printed circuit board (PCB) routing. Interface modes support from 2 to 8 lanes and SerDes linerates up to 17.16 Gbps to allow the optimal configuration for each application.

Features

• Qualified for automotive applications
• ADC Core:
• Resolution: 9 Bit
• Maximum sampling rate: 1.3 GSPS
• Non-interleaved architecture
• Internal dither reduces high-order harmonics
• Performance specifications (–1 dBFS):
• SNR (100 MHz): 53.5 dBFS
• ENOB (100 MHz): 8.5 Bits
• SFDR (100 MHz): 64 dBc
• Noise floor (–20 dBFS): –143 dBFS
• Full-scale input voltage: 800 mVPP-DIFF
• Full-power input bandwidth: 6 GHz
• JESD204C Serial data interface:
• Support for 2 to 8 total SerDes lanes
• Maximum linerate: 17.16 Gbps
• 64B/66B and 8B/10B encoding modes
• Subclass-1 support for deterministic latency
• Compatible with JESD204B receivers
• Optional internal sampling clock generation
• Internal PLL and VCO
• VCO frequency: 7.2–8.2 GHz
• SYSREF Windowing eases synchronization
• Four clock outputs simplify system clocking
• Reference clocks for FPGA or adjacent ADC
• Reference clock for SerDes transceivers
• Timestamp input and output for pulsed systems
• Power consumption (1 GSPS): 435 mW / channel
• Power supplies: 1.1 V, 1.9 V

Typical applications

• Handheld test equipment, multi-channel oscilloscopes and digitizers, wireless communication and test equipment, optical coherent tomography
• Light detection and ranging (LiDAR)

More information

• Datasheet
• IC product information