Topology | Buck Converter |
Input voltage | 12 V |
Output 1 | 1.2 V |
IC revision | A |
This system level design shows how two ADC12J4000 evaluation modules (EVMs) can be synchronized together using a Xilinx VC707 platform. The design document describes the required hardware modifications and device configurations, including the clocking scheme. Example configuration files are shown for each EVM. The FPGA firmware is described and the relevant Xilinx IP block configuration parameters are shown. Data taken on the actual hardware is shown and analyzed, showing synchronization within 50 ps without characterized cables or calibrated propagation delays.
Order Code | Datasheet | Simulation | Downloads | Status | Product series | L (µH) | IRP,40K (A) | ISAT,10% (A) | ISAT,30% (A) | RDC (mΩ) | fres (MHz) | Material | Samples | |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
744325550 | SPEC PCN pendingDue to a pending PCN there will be a new datasheet revision issued for this order code soon. Please find the actual as well based on valid PCN date the new revision datasheet below. If you have further questions please get in contact with our sales staff. | 8 files | Active i| Production is active. Expected lifetime: >10 years. | WE-HCI SMT Flat Wire High Current Inductor | 5.5 | 12 | 4.5 | 12 | 10.3 | 30 | Superflux |
Order Code | Datasheet | Simulation | |
---|---|---|---|
744325550 | SPEC PCN pendingDue to a pending PCN there will be a new datasheet revision issued for this order code soon. Please find the actual as well based on valid PCN date the new revision datasheet below. If you have further questions please get in contact with our sales staff. |
Samples |
---|
Order Code | Datasheet | Simulation | Downloads | Status | Product series | L (µH) | IRP,40K (A) | ISAT,10% (A) | ISAT,30% (A) | RDC (mΩ) | fres (MHz) | Material | Samples |
---|